A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
1. Field of the Invention
The present invention relates to a communications circuit, and in particular, to an interface circuit permitting communication between circuits utilizing dissimilar logic families without requiring level translation.
2. Description of the Related Art
The Electronic Industry Association (EIA) and the Telecommunications Industry Association (TIA) are industry trade associations that have developed standards to simplify data communications. The TIA/EIA-232 (RS232) is one of the oldest and most widely known communication standards. It describes an unbalanced, unidirectional, point-to point interface. The RS232 communication standard has periodically been updated, with the latest revision being RS232-G.
The RS232 standard recognizes differential voltage signals ranging from xe2x88x9212V to +12V. At the time of adoption of the RS232 standard, the xc2x112V range provided a voltage spectrum broad enough to permit a variety of analog functions to be performed while the resulting signal remained comfortably above background noise. Of course, RS232 circuits were also utilized in digital applications, and an RS232 truth table is given below in TABLE A:
While the RS232 standard was once prevalent, over time the widespread use of digital technology dictated the implementation of logic families having voltage ranges different than that of the RS232. For example, reduced voltage ranges became available due to improvement in hardware having reduced background noise levels. Lower voltage ranges were also useful in preserving the thin and fragile gate dielectric structures of MOS devices increasingly employed in digital applications.
Accordingly more recently implemented logic families utilize a narrower, single-ended voltage range. Voltage signals in these logic families are compatible with the requirements of MOS transistor operation, and reflect reduced noise levels typically encountered in existing digital technology. One such logic family is the transistor-transistor-logic family (TTL). A truth table for TTL is shown below in TABLE B:
In recent years, several factors have prompted adoption of logic families featuring even narrower voltage ranges than the TTL logic family. One factor is an increased emphasis on portable applications requiring reduced power consumption in order to conserve battery life. Another factor is the ever-shrinking size of MOS devices and the corresponding need to preserve the integrity of thin gate dielectric structures in the presence of applied voltages.
While technology is evolving away from the RS232 communications standard, this standard is still employed in a wide variety of applications. Therefore, there is a need in the art for an interface circuit permitting communication to occur between devices utilizing the RS232 standard and devices utilizing the various other logic families.
FIG. 1 shows a schematic diagram of a conventional interface circuit positioned between a host device featuring an RS232 port, and a peripheral device controlled by a microcontroller utilizing the TTL logic family. Communication circuit 100 includes host device 101 featuring RS232 port 102 having transmit data (TXD) pin 104 and receive data (RXD) pin 106. TXD pin 104 and RXD pin 106 emit and receive, respectively, signals in which between +3V and +12V are interpreted as a logical low state (=0) and between xe2x88x923V and xe2x88x9212V are interpreted as a logical high state (=1).
TTL microcontroller 107 of peripheral device 108 features eight pin parallel port 109. Pins 110 of port 109 emit and receive respectively, voltage signals where between 0V and +0.8V represents a logical low state (=0) and between +2.4V and +5V represents a logical high state (=1).
In order to permit communication to occur between host device 101 and peripheral device 107 interface circuit 100 further includes level shift/buffer 116 and universal asynchronous receiver/transmitter (UART) 118.
The role of level shift/buffer 116 is to perform level translation on the voltage signals being exchanged between host device 101 and peripheral device 107, such that voltage signals correlating to appropriate logic values are communicated between the devices. Thus, where a logical low (+0V) TTL signal is being transmitted from pin 112 of TTL peripheral device 107, level shift/buffer 116 converts this signal to the +12V logical low value understood by RS232 device 101. Conversely, where a logical high value of xe2x88x9212V is being transmitted from RS232 port 102, level shift/buffer 116 converts this signal to the +5V logical high value understood by TTL peripheral device 107. A level shift/buffer commonly employed for this purpose is National Semiconductor Corporation part No. DS14C535, which requires connection to power supplies of both the +5V and +12V variety.
The role played by UART 118 in permitting communication between the RS232 and non RS232 devices two-fold.
UART 118 performs serial-to-parallel or parallel to serial conversion of signals exchanged between host RS232 device 101 and peripheral TTL device 107, such that each device receives a signal in the appropriate form. Thus UART 118 assembles a serial stream of one-bit signals transmitted from RS232 port 102, into discrete eight-bit words recognized at parallel port 109 by peripheral device 107. Conversely, where an eight-bit data word is being transmitted in parallel form from pins 110 of peripheral device 107, UART 118 converts this parallel word into a serial stream of one-bit signals recognized at RS232 port 102 of host device 101. A UART commonly employed for use in interface applications is National Semiconductor Corporation part No. PC16550D.
The second function performed by UART 118 is to coordinate timing of transmission of the serial stream of electrical signals between the devices. Upon receiving a START bit from a transmitting device, UART 118 synchronizes receipt of the serial data stream at regular, predetermined intervals, enabling the serial data to be properly recognized.
While the conventional communication interface circuit shown in FIG. 1 is suitable for some applications, it suffers from a number of disadvantages. One disadvantage is a high part count. Specifically, the conventional interface circuit requires separate level shift/buffer and UART components described above. These components each contribute expense and complexity to the interface. circuit. Another disadvantage of the conventional circuit is that the level/shift buffer component must be connected with power supplies of both devices in order to perform level translation. A further disadvantage is that the UART component is typically bulky and consumes precious space on the circuit board.
Therefore, there is a need in the art for a compact, simple, and inexpensive communication interface circuit between devices utilizing different logic families which does not require separate components to perform level translation and parallel/serial conversion.
The present invention is a communications interface circuit enabling communication between devices utilizing dissimilar logic families, without requiring level translation. Proper conversion of the voltage level of exchanged signals is accomplished by interposing a switching transistor between the two devices.
Taking advantage of a receiver threshold value of a first device, selective activation of the switching transistor permits a voltage signal in excess of the receiver threshold voltage to be transmitted from a second device to the first device. This voltage signal is interpreted by the first device as the correct logic level.
In another aspect of the present invention, the first device transmits a default voltage from the transmit pin while receiving a voltage on the receiver pin. Taking advantage of this property, selective deactivation of the switching transistor isolates the first device from the second device, permitting the default voltage signal output from the transmit data pin of the first device to be returned back to the receive data pin the same (first) device.
An apparatus including a communication interface circuit in accordance with a first embodiment of the present invention comprises a first device including a first receive data terminal, a first transmit data terminal, a first power supply terminal configured to convey a first:power supply voltage, and a second power supply terminal configured to convey a second power supply voltage. A second device includes a third power supply terminal configured to bear a third power supply voltage different from the first power supply voltage, a fourth power supply terminal configured to bear a fourth power supply voltage different from the second power supply voltage, a second receive data terminal configured to convey a received data signal, and a second transmit data terminal configured to convey a default voltage while the second receive data terminal receives a data signal. The second device interprets the received data signal traversing a receiver threshold value as a first logic state and interpreting the received data signal not traversing the receiver threshold value as a second logic state opposite the first logic state, the first power supply voltage traversing the receiver threshold value. A switch includes a first node, a second node, and a control node. The first node is in electrical communication with the first transmit data terminal, the second transmit data terminal, and the second receive data terminal. The second node is in electrical communication with the first power supply terminal, and the control node in electrical communication with the first receive data terminal. The switch is configured to a first state to convey the first power supply voltage to the second receive data terminal, and the switch is configured to a second state to convey the default voltage signal from the second transmit data terminal to the second receive data terminal, and to convey a voltage signal from the second transmit data terminal to the first receive data terminal.
A method in accordance with one embodiment of the present invention for communicating between a first device utilizing a first logic family and a second device utilizing a second logic family different from the first logic family comprises the steps of forming an electrical connection between a first node of a switch and a transmit data terminal of the first device. An electrical connection is formed between the first switch node and a transmit data terminal of the second device. An electrical connection is formed between the first switch node and a receive data terminal of the second device, and an electrical connection is formed between a second node of the switch and a power supply of the first device. An electrical connection is formed between a control node of the switch and a receive data terminal of the first device. A first power supply voltage is transmitted from the receive data terminal of the first device to the switch control node, such that the switch is placed into a first state and a second power supply voltage is conveyed from the transmit data terminal of the second device to the transmit data terminal of the first device. The first power supply voltage is transmitted from the receive data terminal of the first device to the switch control node, such that the switch is placed into the first state and a third power supply voltage is conveyed from the transmit data terminal of the second device to the receive data terminal of the second device. A fourth power supply voltage is transmitted from the receive data pin of the first device to the switch control node, such that the switch is placed into a second state and the first power supply voltage is conveyed from the first device to the receive data pin of the second device, the second device interpreting the received first power supply voltage traversing a receiver threshold value as a first logic state.